The present invention relates to integrated circuits (IC) and, more particularly, to IC diodes, such as those used for electro-static discharge (ESD) protection.
An integrated circuit is fabricated by selectively adding material to and removing material from a semiconductor substrate in a sequence of fabrication steps. For example, p (positive) or n (negative) doped well regions are formed on a substrate by masking regions that are to remain undoped and then applying an appropriate p- or n-type dopant material to form p/n wells in the remaining unmasked regions. During such a fabrication step, the p/n wells will all be formed to have the same thickness (aka depth), which thickness is dictated by the requirements of the desired integrated circuitry.
One known type of integrated circuitry is ESD-protection circuitry, which is designed to protect other circuitry formed on the same substrate from electro-static discharge (ESD) events during which an over voltage (e.g., a voltage sufficiently higher than the IC high supply voltage VDD) or an under voltage (e.g., a voltage sufficiently lower than the IC low supply voltage VSS) is applied to an input/output (I/O) port (aka I/O pin or I/O pad) of the IC.
FIG. 1 is a schematic circuit diagram of one known type of ESD-protection circuitry 100 configured to protect other (i.e., protected) circuitry 120 from ESD events at an I/O pin 130. As shown in FIG. 1, the ESD-protection circuitry 100 has a first diode 112 connected between VSS and the I/O pin 130 and a second diode 114 connected between the I/O pin 130 and VDD. During normal operations in which the voltage level applied to the I/O pin 130 remains at or above the low supply voltage level VSS and at or below the high supply voltage level VDD, neither the first diode 112 nor the second diode 114 will conduct current.
If and when, however, the voltage level applied to the I/O pin 130 begins to fall below VSS by one diode voltage drop (˜0.7V), current will begin to flow through the first diode 112 from VSS to the I/O pin 130, thereby limiting the magnitude of the under voltage condition at the I/O pin 130 and preventing an undesirably large under voltage from being applied to the protected circuitry 120. Similarly, if and when the voltage level applied to the I/O pin 130 begins to exceed VDD by one diode voltage drop (˜0.7V), current will begin to flow through the second diode 114 from the I/O pin 130 to VDD, thereby limiting the magnitude of the over voltage condition at the I/O pin 130 and preventing an undesirably large over voltage from being applied to the protected circuitry 120. In order to provide adequate ESD protection to the protected circuitry 120, the diodes 112 and 114 must be designed and configured to rapidly shunt sufficiently large amounts of current away from the I/O pin 130.
FIG. 2 is a cross-sectional side view of the region of a semiconductor substrate 202 corresponding to a conventional N+/isolated P well gated diode 200 that can be used to implement the first diode 112 of FIG. 1. Those skilled in the art will understand that an analogous P+/N well gated diode can be used to implement the second diode 114 of FIG. 1.
As represented in FIG. 2, the gated diode 200 has six diode fingers 210(1)-210(6), each comprising a dielectric gate 212 above and separating a P+ diffusion 214 from an adjacent N+ diffusion 216. Note that, except for the outermost P+ diffusion 214(1) and 214(4), each of the P+ and N+ diffusions 214 and 216 is shared by two adjacent fingers 210. For example, the N+ diffusion 216(1) is shared by the fingers 210(1) and 210(2), the P+ diffusion 214(2) is shared by the fingers 210(2) and 210(3), and so on.
As represented in FIG. 2, each P+ diffusion 214 is connected by way of a corresponding conducting (e.g., metal) contact 218 to VSS, and each N+ diffusion 216 is connected by way of a corresponding contact 218 to a corresponding I/O pin (e.g., the I/O pin 130 of FIG. 1). Although not shown in FIG. 2, each gate 212 is connected to its corresponding P+ diffusion 214. Thus, the gate 212(1) is connected to the P+ diffusion 214(1), the gates 212(2) and 212(3) are both connected to the shared P+ diffusion 214(2), the gates 212(4) and 212(5) are both connected to the shared P+ diffusion 214(3), and the gate 212(6) is connected to the P+ diffusion 214(4).
If and when the voltage applied to the I/O pin begins to fall below VSS by one diode voltage drop (˜0.7V), current will begin to flow from the P+ diffusions 214 to the N+ diffusions 216, as represented by the horizontal arrows in FIG. 2. The magnitude of the maximum current that can flow within the gated diode 200 is a function of, among other things, the number of fingers 210 in the gated diode 200 and the lateral surface area of the side walls of each of the P+ and N+ diffusions 214 and 216. The lateral surface area of each diffusion is a function of the thickness of the diffusions.
In typical IC fabrication procedures, a single fabrication step is used to form a number of P+ diffusions on the semiconductor substrate such that all of those P+ diffusions have the same thickness. Similarly, another fabrication step is used to form a number of N+ diffusions on the semiconductor substrate such that all of those N+ diffusions have the same thickness, which is typically but not necessarily the same as the thickness of the P+ diffusions.
In a typical IC, the thickness of the N+ and P+ diffusions in a gated diode, such as the gated diode 200 of FIG. 2, is dictated by the requirements of other (i.e., non-ESD-protection) circuitry formed on the same semiconductor substrate. As such, since the thickness of the P+ and N+ diffusions is fixed by those other requirements, in order to enable a gated diode having the architecture of the gated diode 200 to support a sufficient amount of current for ESD protection, the gated diode must be designed with a sufficient number of fingers, with larger maximum current levels requiring more fingers and therefore larger footprints on the semiconductor substrate for those gated diodes.
It would be advantageous to have a gated diode for ESD protection devices that does not require an excessive amount of substrate real estate.